This invention relates to error detection and correction circuitry and, more particularly, to the use of error detection and correction circuitry in data communications over high-speed serial communication links.
Integrated circuits communicate with one another via communication paths sometimes also known as input-output (I/O) buses. An increasingly important communications type is data communication in the form of serial data streams over serial communication links. Serial communication can be faster than parallel communications and typically uses fewer pins.
It can be challenging to handle serial data streams at high data rates (e.g., at data rates above several Gbps) especially if communication links are subject to channel noise which may result in the introduction of errors during the transmission of the serial data stream from a transmitter over the communication link to a receiver. As a result, serial links often use error checking schemes such as the cyclic redundancy checking (CRC) error checking scheme or the Reed Solomon error correction scheme.
The implementation of error checking schemes typically involves a significant increase in circuit size and latency. Consequently, it is desirable to provide improved mechanisms for implementing error correction.